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integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 rev. a 03/17/06 issi ? copyright ? 2006 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtai n the latest version of this device specification before relying on any published information and before placing orders for products. is65c256al is62c256al features ? access time: 25 ns, 45 ns ? low active power: 200 mw (typical) ? low standby power ? 150 w (typical) cmos standby ? 15 mw (typical) operating ? fully static operation: no clock or refresh required ? ttl compatible inputs and outputs ? single 5v power supply ? lead-free available ? industrial and automotive temperatures avail- able description the issi is62c256al/is65c256al is a low power, 32,768 word by 8-bit cmos static ram. it is fabricated using issi 's high-performance, low power cmos tech- nology. when ce is high (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 150 w (typical) at cmos input levels. easy memory expansion is provided by using an active low chip select ( ce ) input and an active low output enable ( oe ) input. the active low write enable ( we ) controls both writing and reading of the memory. the is62c256al/is65c256al is pin compatible with other 32kx8 srams in plastic sop or tsop (type i) package. functional block diagram a0-a14 ce oe we 32k x 8 memory array decoder column i/o control circuit gnd vdd i/o data circuit i/o0-i/o7 32k x 8 low power cmos static ram march 2006
2 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 03/17/06 issi ? is65c256al is62c256al pin configuration 28-pin sop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd vdd we a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd ?0.5 to +7.0 v t stg storage temperature ?65 to +150 c p t power dissipation 0.5 w i out dc output current (low) 20 ma note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 1 9 18 17 16 15 14 13 12 11 10 9 8 oe a11 a 9 a8 a13 we vdd a14 a12 a7 a6 a5 a4 a3 a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 pin configuration 28-pin tsop pin descriptions a0-a14 address inputs ce chip select input oe output enable input we write enable input i/o0-i/o7 input/output v dd power gnd ground truth table mode we we we we we ce ce ce ce ce oe oe oe oe oe i/o operation v dd current not selected x h x high-z i sb 1 , i sb 2 (power-down) output disabled h l h high-z i cc 1 , i cc 2 read h l l d out i cc 1 , i cc 2 write l l x d in i cc 1 , i cc 2
integrated silicon solution, inc. ? 1-800-379-4774 3 rev. a 03/17/06 issi ? is65c256al is62c256al operating range part no. range ambient temperature v dd is62c256al commercial 0c to +70c 5v 10% is62c256al industrial ?40c to +85c 5v 10% is65c256al automotive ?40c to +125c 5v 10% dc electrical characteristics symbol parameter test conditions mi n. max. unit v oh output high voltage v dd = min., i oh = ?1.0 ma 2.4 ? v v ol output low voltage v dd = min., i ol = 2.1 ma ? 0.4 v v ih input high voltage 2.2 v dd + 0.5 v v il input low voltage (1) ?0.3 0.8 v i li input leakage gnd v in v dd com. ?1 1 a ind. ?2 2 auto. ?10 10 i lo output leakage gnd v out v dd , com. ?1 1 a outputs disabled ind. ?2 2 auto. ?10 10 note: 1. v il = ?3.0v for pulse width less than 10 ns.
4 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 03/17/06 issi ? is65c256al is62c256al capacitance (1,2) symbol parameter cond itions max. unit c in input capacitance v in = 0v 8 pf c out output capacitance v out = 0v 10 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 5.0v. power supply characteristics (1) (over operating range) -25 ns -45 ns symbol parameter test conditions min. max. min. max. unit i cc 1 v dd operating v dd = max., ce = v il com. ? 15 ? 15 ma supply current i out = 0 ma, f = 0 ind. ? 20 ? 20 auto. ? 25 ? 25 i cc 2 v dd dynamic operating v dd = max., ce = v il com. ? 25 ? 20 ma supply current i out = 0 ma, f = f max ind. ? 30 ? 25 auto. ? 35 ? 30 typ. (2) 15 12 i sb 1 ttl standby current v dd = max., com. ? 100 ? 100 a (ttl inputs) v in = v ih or v il ind. ? 120 ? 120 ce v ih , f = 0 auto. ? 150 ? 150 i sb 2 cmos standby v dd = max., com. ? 15 ? 15 a current (cmos inputs) ce v dd ? 0.2v, ind. ? 20 ? 20 v in v dd ? 0.2v, or auto. ? 50 ? 50 v in 0.2v, f = 0 typ. (2) 5 5 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd = 5.0v, t a = 25 o c and not 100% tested.
integrated silicon solution, inc. ? 1-800-379-4774 5 rev. a 03/17/06 issi ? is65c256al is62c256al figure 1. figure 2. 480 5 pf including jig and scope 255 output 5v ac test loads ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 3 ns input and output timing 1.5v and reference levels output load see figures 1 and 2 read cycle switching characteristics (1) (over operating range) -25 ns -45 ns symbol parameter min. max. min. max. unit t rc read cycle time 25 ? 45 ? ns t aa address access time ? 25 ? 45 ns t oha output hold time 2 ? 2 ? ns t acs ce access time ? 25 ? 45 ns t doe oe access time ? 13 ? 25 ns t lzoe (2) oe to low-z output 0 ? 0 ? ns t hzoe (2) oe to high-z output 0 12 0 20 ns t lzcs (2) ce to low-z output 3 ? 3 ? ns t hzcs (2) ce to high-z output 0 12 0 20 ns t pu (3) ce to power-up 0 ? 0 ? ns t pd (3) ce to power-down ? 20 ? 30 ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. not 100% tested. 480 100 pf including jig and scope 255 output 5v
6 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 03/17/06 issi ? is65c256al is62c256al read cycle no. 2 (1,3) ac waveforms read cycle no. 1 (1,2) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , ce = v il . 3. address is valid prior to or coincident with ce low transitions. data valid read1.eps previous data valid t aa t oha t oha t rc d out address t rc t oha t aa t doe t lzoe t acs t lzcs t hzoe high-z data valid address oe ce d out t hzcs cs_rd2.eps
integrated silicon solution, inc. ? 1-800-379-4774 7 rev. a 03/17/06 issi ? is65c256al is62c256al write cycle switching characteristics (1,3) (over operating range) -25 ns -45 ns symbol parameter min. max. min. max. unit t wc write cycle time 25 ? 45 ? ns t scs ce to write end 15 ? 35 ? ns t aw address setup time to write end 15 ? 25 ? ns t ha address hold from write end 0 ? 0 ? ns t sa address setup time 0 ? 0 ? ns t pwe 1, we pulse width 15 ? 25 ? ns t pwe 2 (4) t sd data setup to write end 12 ? 20 ? ns t hd data hold from write end 0 ? 0 ? ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defined by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falli ng edge of the signal that terminates the write. 4. tested with oe high. ac waveforms write cycle no. 1 ( ce controlled, oe is high or low) (1 ) data undefined t wc valid address t scs t pwe1 t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in data in valid t lzwe t sd cs_wr1.eps
8 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 03/17/06 issi ? is65c256al is62c256al ac waveforms write cycle no. 2 ( oe is high during write cycle) (1,2) write cycle no. 3 ( oe is low during write cycle) (1) notes: 1. the internal write time is defined by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falli ng edge of the signal that terminates the write. 2. i/o will assume the high-z state if oe = v ih . data undefined low t wc valid address t pwe1 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd cs_wr2.eps data undefined t wc valid address low low t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd cs_wr3.eps
integrated silicon solution, inc. ? 1-800-379-4774 9 rev. a 03/17/06 issi ? is65c256al is62c256al data retention switching characteristics symbol parameter test condition min. typ. max. unit v dr v dd for data retention see data retention waveform 2.0 5.5 v i dr data retention current v dd = 2.0v, ce v dd ? 0.2v com. ? ? 15 a v in v dd ? 0.2v, or v in v ss + 0.2v ind. ? ? 20 auto. ? ? 50 t sdr data retention setup time see data retention waveform 0 ? ns t rdr recovery time see data retention waveform t rc ?ns note: 1. typical values are measured at v dd = 5v, t a = 25 o c and not 100% tested. data retention waveform ( ce ce ce ce ce controlled) vdd ce vdd - 0.2v t sdr t rdr v dr ce gnd 4.5v 2.2v data retention mode
10 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 03/17/06 issi ? is65c256al is62c256al ordering information commercial range: 0c to +70c speed (ns) order part no. package 45 is62c256al-45t tsop is62c256al-45tl tsop, lead-free is62c256al-45u plastic sop is62c256al-45ul plastic sop, lead-free ordering information industrial range: ?40c to +85c speed (ns) order p art no. package 25 is62c256al-25ti tsop is62c256al-25ui plastic sop 45 is62c256al-45ti tsop is62c256al-45tli tsop, lead-free is62c256al-45ui plastic sop is62c256al-45uli plastic sop, lead-free ordering information automotive range: ?40c to +125c speed (ns) order part no. package 25 is65c256al-25ta3 tsop is65c256al-25tla3 tsop, lead-free IS65C256AL-25UA3 plastic sop is65c256al-25ula3 plastic sop, lead-free 45 is65c256al-45ta3 tsop is65c256al-45tla3 tsop, lead-free is65c256al-45ua3 plastic sop is65c256al-45ula3 plastic sop, lead-free
integrated silicon solution, inc. issi packaging information d seating plane b e c 1 e a1 a s h l a n plastic tsop - 28-pins package code: t (type i) plastic tsop (ttype i) millimeters inches symbol min max min max ref. std. no. leads 28 a 1.00 1.20 0.037 0.047 a1 0.05 0.20 0.002 0.008 b 0.16 0.27 0.006 0.011 c 0.10 0.20 0.004 0.008 d 7.90 8.10 0.308 0.316 e 11.70 11.90 0.456 0.465 h 13.20 13.60 0.515 0.531 e 0.55 bsc 0.022 bsc l 0.30 0.70 0.011 0.027 a 0 5 0 5 notes: 1. controlling dimension: millimeters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e do not include mold flash protrusions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. pk13197t28 rev. b 01/31/97
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. c 02/26/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. 330-mil plastic sop package code: u (28-pin) d seating plane b e c 1 n e1 a1 a e l s h x 45 o notes: 1. controlling dimension: inches, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. millimeters inches sym. min. max. min. max. no. leads 28 28 a ? 2.84 ? 0.112 a1 0.10 ? 0.004 ? b 0.36 0.51 0.014 0.020 c 0.25 ? 0.010 ? d 17.98 18.24 0.708 0.718 e 11.51 12.12 0.453 0.477 e1 8.28 8.53 0.326 0.336 e 1.27 bsc 0.050 bsc h 0.30 0.51 0.012 0.020 l 0.71 1.14 0.028 0.045 0 o 8 o 0 o 8 o s 0.58 1.19 0.023 0.047

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